Hardware Changes
The major changes in hardware are the following:
Camera Link Connectors
- The camera link connectors MDR26 on mE4 frame grabbers are replaced by SDR26 connectors on mE5 marathon frame grabbers.
SDR Cables Required |
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As mE5 marathon frame grabbers provide SDR26 Camera Link connectors, you need to replace the cable connecting the camera with the frame grabber. Make sure you select an SDR cable that can be run with the required pixel clock. |
Two GPIO Connectors
- The GPIO connector you use for connecting a trigger board or another frame grabber remains exactly the same.
- In addition, mE5 marathon frame grabbers are extended by a second GPIO bank (the Front GPIO). The Front GPIO) is available on the slot bracket of mE 5 frame grabbers.
- The Front GPIO may allow you to replace the trigger extension board you have used with your mE4 frame grabber. In many cases, you can directly use the pins of Front GPIO on the slot bracket of mE5 marathon frame grabbers instead.
- However, you can still use all trigger extension boards Opto Trigger IV and TTL you used with microEnable 4, as well as the new trigger extension board Opto Trigger 5. The trigger boards are connected to the frame grabber like on mE4 frame grabbers via the GPIO connector.
PCIe Slot Requirements
- To achieve the full performance of mE5 marathon frame grabbers, you should use a PCIe Gen. 2 x4 slot.
- Due to the use of PCIe Gen2 x4, bandwidth is increased in comparison to AD1, AS1 or VD1.
- However, you can also use Gen1 slots and/or slots with only one lane (x1) without problems. However, mind that in such a case
- the mE5 marathon frame grabber will run at slower speeds.
- you need to ensure that the x1 slot can physically hold x4 cards (slot size).
Further information on PCIe Generations and Slot SizesThe bandwidth available for an individual frame grabber board depends on various factors:
Physical size of used PCIe slot (PCIe x1, PCIe x4, PCIe x8, or PCIe x16)
On motherboards, you may find a variety of PCIe slot sizes. The images below depict the individual slot sizes and the matching PCIe plugs on the extension boards (for example, frame grabber boards).
The slots are downward compatible, that is, you can plug a PCIe x1 plug into a PCIe x1, x4, x8, or x16 slot. You can as well plug a PCIe x4 plut into a PCIe x4, x8, or x16 slot, and so on. However, you will not be able to plug a bigger PCIe plug into a smaller PCIe slot.
Slot Sizes: Plug Sizes:
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Various slot sizes available on mother boards1
Plug sizes available on extension boards like frame grabbers
Keep in mind that a physically small slot may offer the same performance as a physically big slot. See the other bandwidth factors below for details.
Maximum number of active PCIe lanes (PCIe links) supported by the used PCIe slot
A PCIe x16 slot may provide up to 16 wired PCIe lanes. A PCIe x 8 slot may provide a maximum of 8 wired PCIe lanes, a PCIe x4 slot maximally 4 wired PCIe lanes, and a PCIe x1 slot only provides 1 wired PCIe lane.
Attention! A PCIe slot may provide less wired lanes than its size allows. For example, a PCIe slot with size x16 (see figures above) may only provide 8 wired lanes. For information on how many lanes are provided by a specific PCIe slot, refer to the manual of your motherboard.
Physical size of PCIe slot x1 x4 x8 x16 Possible
number
of wired PCIe
lanes1 yes yes yes yes 4 no yes yes yes 8 no no yes yes 16 no no no yes
PCIe generation supported by the used PCIe slot
Each PCIe slot on your motherboard supports a specific max. PCIe generation. Refer to your motherboard manual to find out which PCIe generation the individual PCIe slots on your motherboard support.
Each PCIe generation offers a specific theoretical bandwidth per PCIe lane:
PCIe 1.x: 0.25 GB/s (2Gbps)
PCIe 2.x: 0.50 GB/s (4Gbps)
PCIe 3.x: 0.985 GB/s (7.88Gbps)
Burstrates in GBytes/s without protocoll overhead:2
Number
of LanesPCIe 1.0/1.1 PCIe 2.0/2.1 PCIe 3.0/3.1 x1 0.25 0.5 0.985 x4 1.0 2.0 3.938 x8 2.0 4.0 7.877 x16 4.0 8.0 15.754
Maximum number of active PCIe lanes supported by CPU and Chipsets of the host PC
Each CPU and/or chipset offers a maximum of active PCIe lanes. You cannot use more PCIe lanes than offered by the CPU/chipset.
Attention! Even if you have a CPU or chipset offering, for example, 32 PCIe lanes, this doesn't automatically mean you can work four x8 frame grabbers at full speed using these links, as some of the CPU's PCIe lanes may be used for other purposes (like NVMe). Refer to your CPU and motherboard manuals for details.
Payload size
Some BIOS offer a setting option for the payload size. A value higher than 128 bytes can positively influence the performance of the frame grabber. If the performance is improved, the information "High speed PCIe capable" is displayed in microDiagnostics for the board plugged into the according PCIe slot.
Power and Temperature
- mE5 marathon frame grabbers use passive cooling (like mE4 frame grabbers). The typical power dissipation is 12W. When you receive a mE5 marathon frame grabber, the heatsink is already mounted.
- The operating temperature has been increased to 50°C. With an air flow of 100 linear feet per minute you can even use 60°C.
- Ensure sufficient air flow in the host PC.
- Compare the environment conditions with the requirements for the mE5 marathon frame grabber board you are going to use:
mE5 marathon ACL
marathon ACL
Host Interface
PCIe Gen 2 x4 (Direct Memory Access)
Bandwidth (theor.)
2 GB/s
Bandwidth (typ./max.)
Up to 1.8 GB/s sustainable data bandwidth
(maximal Camera Link data rate 850 MByte/s)On-board memory 512 MByte DDR3-RAM On-board FPGA
processing capabilitiesAcquisition Applets Voltage, typ. current
(actual values depend
on processing)12 V, 1 A Max. slew rate of input voltage3
6V/ms
Dimensions PCIe standard height, half length card:
167.64 mm length x 111.15 mm heightWeight 200g Camera interface 2 x Camera Link xx standard (2 * SDR 26) (mini CL) Ambient temperature 50° (0 LFM*)
60° (100 LFM)
An adequate airflow in the PC is recommended.FPGA operating temperature** 0°C to 85°C Storage temperature -50°C up to +80°C Relative humidity 5% - 90% non-condensing (operating), 0% - 95% (storage) Conformity CE, RoHS * LFM = Linear Feet per Minute, unit for measuring airflow velocity.
** Temperature being meassured directly on the FPGA; the meassured value can be read out in all applets available for Runtime Software via applet parameter FG_SYSTEMMONITOR_FPGA_TEMPERATURE.
mE5 marathon VCL
marathon VCL
Host Interface
PCIe Gen 2 x4 (Direct Memory Access)
Bandwidth (theor.)
1x1800 MB/s
Bandwidth (typ./max.)
Up to 1800 MB/s sustainable data bandwidth
(= maximal Camera Link data rate)On-board memory 2GByte DDR3-RAM On-board FPGA
processing capabilitiesAcquisition Applets,
VA Applets,
Smart AppletsVoltage, typ. current
(actual values depend
on processing)12 V, 1 A Max. slew rate of input voltage4
6V/ms
Dimensions PCIe standard height, half length card:
167.64 mm length x 111.15 mm heightWeight 200g Camera interface 2 x Camera Link xx standard (2 * SDR 26) (mini CL) Ambient temperature 50° (0 LFM*)
60° (100 LFM)
An adequate airflow in the PC is recommended.FPGA operating temperature** 0°C to 85°C Storage temperature -50°C up to +80°C Relative humidity 5% - 90% non-condensing (operating), 0% - 95% (storage) Conformity CE, RoHS * LFM = Linear Feet per Minute, unit for measuring airflow velocity.
** Temperature being meassured directly on the FPGA; the meassured value can be read out in all applets available for Runtime Software via applet parameter FG_SYSTEMMONITOR_FPGA_TEMPERATURE.
- There is a new applet parameter available (in all applets for mE5 marathon frame grabbers) that provides information on the FPGA temperature. The name of the parameter is FG_SYSTEMMONITOR_FPGA_TEMPERATURE.
Power over Camera Link (PoCL)
- mE5 marathon Camera Link frame grabbers support Power over Camera Link (PoCL).
- The frame grabber does not need an extra power connector. It will use the PCIe power for PoCL.
- You need to enable PoCL in microDiagnostics if you want to use it.
Enabling PoCLTo enable PoCL support for using a PoCL camera:
- Open the tool microDiagnostics, which comes as part of the runtime installation (installation directory, subdirectory bin).
- In the Frame Grabber pane of microDiagnostics, select the board you want to enable the PoCL support for.
- From the Tools menu, select Board Settings.
- In the dialog, select Enable PoCL Detection.
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- Re-configure the FPGA on the frame grabber. To do so, you can either
- activate/load another applet, or
- cold-boot your host PC.
Now, PoCL support on Runtime Software is enabled.
Board Size
The board size remains exactly the same: PCIe standard height, half length card (167.64 mm length x 111.15 mm height).
Detailed Information on Replacement Boards |
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For more detailed information on the recommended replacements of your mE4 frame grabber, refer to the respective frame grabber manual in our online documentation: |