Workflow

To get a first impression on how to work with VisualApplets, find below a description of the essential steps required to generate an image processing application with VisualApplets. You will learn how fast applications can be realized in VisualApplets without any knowledge of hardware description languages.

For detailed instructions, refer to our comprehensive VisualApplets documentation.

Step 1

You start a new project by creating a new project file.

VisualApplets will now start a new project. You will see a blank1 design area in the center of your program window. In the information panel on the right, you get information regarding your current project like project name, target hardware, target platform.

Empty Design in VisualApplets

Step 2

You select operators, combine them to form your individual design, and link them to each other.

In VisualApplets, image processing operations are represented by operators. All these operators can be found in the operator library. Using drag-and-drop, you can very easily place operator instances into the design area.

Operators can have input and output ports. The input ports are always on the left-hand side, the output ports on the right-hand side. Use this ports to connect operator instances with each other (by clicking on one port and than on the second port of a link). Connections between operator instances are called links which are represented in the design window by arrows:

Operator instances and links together represent the image- (or signal-) processing pipeline; hence, the order of operations is determined by the order of operator instances and their linking.

Step 3

You parameterize your operators and links. (Otherwise, the design will use the preset default properties.)

Parameters of an operator instance

Parameters are always operator-specific; therefore, the setting options differ from operator to operator. To open the Module Properties window for operator parameterization, or the Link Properties window for link parameterization, just double-click on the operator instance/link in your design.

Parameters of a link between two operator instances

Step 4

Run the Design Rules Check (DRC).

You check your design for errors, using the Design Rules Check function of VisualApplets.

You simply have to click the according button , and the Design Rules Check will be run by VisualApplets.

In the Project Info window on the right, the DRC analysis results are displayed:

Successful DRC

If the DRC detects an error, you have to correct it before continuing with the next step. Detected errors are listed in link format. If you click on one of the listed errors, the respective module or link will be highlighted in the Design Window.

Step 5

You build the final executable hardware applet via mouse click.

VisualApplets will translate the application into the FPGA bitstream, i.e., the "program" or "applet".

After successful build, the applet is fully generated. It is saved automatically as a *.hap file to the default build output folder

[VisualApplets installation directory]/Designs

or an individual folder you can specify before you started the build.

At this point, you are done with VisualApplets and can use the applet in real FPGA hardware. To learn how to do this, proceed with Running your Applet on Hardware .