Architecthure

The CLIO modules copy all frames received by the microEnable IV CameraLink port to the output. The module copies all image data (D00..D23), Strobes (FVAL, LVAL, DVAL, CTRL), and the pixel clock (PCLK). Output generated by the frame grabber (CC1..CC3) and the serial communication (SER2FG, SER2CAM) is NOT copied.

The CLIO module introduces a delay to the CameraLink data stream. In a chain the delay increases proportionally to the number of CLIO modules. For a single module the delay is twice the delay time of the CameraLink interface.

The delay time of the CameraLink ICs (CLIO DS90CR287 / microEnable IV DS90C288) is between 3.8ns and 6.3 ns. In a typical application the worst case delays are approx. one PCLK tick and far less than a typical camera line length. In most situations these delays are negligible.